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1855 lines
68 KiB
Python
1855 lines
68 KiB
Python
"""Porting functionality of MIPS ASM to hex."""
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from enum import IntEnum, auto
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# Based on the codebase of: https://www.eg.bucknell.edu/~csci320/mips_web/
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class opcodeTable(IntEnum):
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"""Opcode Table Enum."""
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SPECIAL = 0
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REGIMM = 1
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J = 2
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JAL = 3
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BEQ = 4
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BNE = 5
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BLEZ = 6
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BGTZ = 7
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ADDI = 8
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ADDIU = 9
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SLTI = 10
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SLTIU = 11
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ANDI = 12
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ORI = 13
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XORI = 14
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LUI = 15
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COP0 = 16
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COP1 = 17
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COP2 = 18
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COP3 = 19
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BEQL = 20
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BNEL = 21
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BLEZL = 22
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BGTZL = 23
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DADDI = 24
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DADDIU = 25
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LB = 32
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LH = 33
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LWL = 34
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LW = 35
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LBU = 36
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LHU = 37
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LWR = 38
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SB = 40
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SH = 41
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SWL = 42
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SW = 43
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SWR = 46
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CACHE = 47
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LLU = 48
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LWC1 = 49
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LWC2 = 50
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LWC3 = 51
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LDC1 = 53
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LDC2 = 54
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LDC3 = 55
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SC = 56
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SWC1 = 57
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SWC2 = 58
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SWC3 = 59
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SDC1 = 61
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SDC2 = 62
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SDC3 = 63
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class functTable(IntEnum):
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"""Function Table Enum."""
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SLL = 0
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SRL = 2
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SRA = 3
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SLLV = 4
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SRLV = 6
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SRAV = 7
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JR = 8
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JALR = 9
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SYSCALL = 12
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BREAK = 13
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MFHI = 16
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MTHI = 17
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MFLO = 18
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MTLO = 19
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DSLLV = 20
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DSRAV = 23
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MULT = 24
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MULTU = 25
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DIV = 26
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DIVU = 27
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DMULT = 28
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DMULTU = 29
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DDIV = 30
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DDIVU = 31
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ADD = 32
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ADDU = 33
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SUB = 34
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SUBU = 35
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AND = 36
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OR = 37
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XOR = 38
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NOR = 39
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SLT = 42
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SLTU = 43
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DADD = 44
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DADDU = 45
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TGE = 48
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TGEU = 49
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TLT = 50
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TLTU = 51
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TEQ = 52
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TNE = 54
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DSLL = 56
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DSRL = 58
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DSRA = 59
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DSLL32 = 60
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DSRL32 = 62
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DSRA32 = 63
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class regimmTable(IntEnum):
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"""RegiMM Table Enum."""
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BLTZ = 0
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BGEZ = 1
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BLTZL = 2
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BGEZL = 3
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TGEI = 8
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TGEIU = 9
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TLTI = 10
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TLTIU = 11
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TEQI = 12
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TNEI = 14
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BLTZAL = 16
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BGEZAL = 17
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BLTZALL = 18
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BGEZALL = 19
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class Reg(IntEnum):
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"""Register Enum."""
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zero = 0
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at = 1
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v0 = 2
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v1 = 3
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a0 = 4
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a1 = 5
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a2 = 6
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a3 = 7
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t0 = 8
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t1 = 9
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t2 = 10
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t3 = 11
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t4 = 12
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t5 = 13
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t6 = 14
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t7 = 15
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s0 = 16
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s1 = 17
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s2 = 18
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s3 = 19
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s4 = 20
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s5 = 21
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s6 = 22
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s7 = 23
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t8 = 24
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t9 = 25
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k0 = 26
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k1 = 27
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gp = 28
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sp = 29
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fp = 30
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ra = 31
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class Symbol(IntEnum):
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"""Instruction Symbol Enum."""
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ADD = auto()
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ADDI = auto()
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ADDIU = auto()
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ADDU = auto()
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AND = auto()
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ANDI = auto()
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BEQ = auto()
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BEQL = auto()
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BGEZ = auto()
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BGEZAL = auto()
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BGEZALL = auto()
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BGEZL = auto()
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BGTZ = auto()
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BGTZL = auto()
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BLEZ = auto()
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BLEZL = auto()
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BLTZ = auto()
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BLTZAL = auto()
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BLTZALL = auto()
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BLTZL = auto()
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BNE = auto()
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BNEL = auto()
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BREAK = auto()
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COP0 = auto()
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COP1 = auto()
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COP2 = auto()
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COP3 = auto()
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DADD = auto()
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DADDI = auto()
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DADDIU = auto()
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DADDU = auto()
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DDIV = auto()
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DDIVU = auto()
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DIV = auto()
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DIVU = auto()
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DMULT = auto()
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DMULTU = auto()
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DSLL = auto()
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DSLL32 = auto()
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DSLLV = auto()
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DSRA = auto()
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DSRA32 = auto()
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DSRAV = auto()
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DSRL = auto()
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DSRL32 = auto()
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DSRLV = auto()
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DSUB = auto()
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DSUBU = auto()
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J = auto()
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JAL = auto()
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JALR = auto()
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JR = auto()
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LB = auto()
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LBU = auto()
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LD = auto()
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LDC1 = auto()
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LDC2 = auto()
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LDL = auto()
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LDR = auto()
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LH = auto()
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LHU = auto()
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LL = auto()
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LLD = auto()
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LUI = auto()
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LW = auto()
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LWC1 = auto()
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LWC2 = auto()
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LWC3 = auto()
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LWL = auto()
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LWR = auto()
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LWU = auto()
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MFHI = auto()
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MFLO = auto()
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MOVN = auto()
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MOVZ = auto()
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MTHI = auto()
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MTLO = auto()
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MULT = auto()
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MULTU = auto()
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NOP = auto()
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NOR = auto()
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OR = auto()
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ORI = auto()
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PREF = auto()
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SB = auto()
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SC = auto()
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SCD = auto()
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SD = auto()
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SDC1 = auto()
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SDC2 = auto()
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SDL = auto()
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SDR = auto()
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SH = auto()
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SLL = auto()
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SLLV = auto()
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SLT = auto()
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SLTI = auto()
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SLTIU = auto()
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SLTU = auto()
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SRA = auto()
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SRAV = auto()
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SRL = auto()
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SRLV = auto()
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SUB = auto()
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SUBU = auto()
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SW = auto()
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SWC1 = auto()
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SWC2 = auto()
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SWC3 = auto()
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SWL = auto()
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SWR = auto()
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SYNC = auto()
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SYSCALL = auto()
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TEQ = auto()
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TEQI = auto()
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TGE = auto()
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TGEI = auto()
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TGEIU = auto()
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TGEU = auto()
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TLT = auto()
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TLTI = auto()
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TLTIU = auto()
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TLTU = auto()
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TNE = auto()
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TNEI = auto()
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XOR = auto()
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XORI = auto()
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class InstructionSegment(IntEnum):
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"""Instruction Segment Enum."""
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special = auto()
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rs = auto()
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rd = auto()
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rt = auto()
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sa = auto()
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regimm = auto()
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static = auto()
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immediate = auto()
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base = auto()
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offset = auto()
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code = auto()
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cop_fun = auto()
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target = auto()
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hint = auto()
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stype = auto()
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default_segment_value = {
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InstructionSegment.special: 0,
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InstructionSegment.regimm: 1,
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}
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class InstructionBit:
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"""Segment data on an instruction."""
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def __init__(self, start_bit: int, end_bit: int, bit_type: InstructionSegment, value: str = None):
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"""Initialize with given parameters."""
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self.start_bit = start_bit
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self.end_bit = end_bit
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self.size = (self.start_bit - self.end_bit) + 1
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self.filter = (1 << self.size) - 1
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self.bit_type = bit_type
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if isinstance(value, str):
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value = int(value, 2)
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elif self.bit_type == InstructionSegment.static and value is None:
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value = 0
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self.value = value
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class InstructionFormat:
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"""Layout of a written instruction."""
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def __init__(self, instruction: str, segments: str):
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"""Initialize with given parameters."""
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self.instruction = instruction
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self.segments = segments
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class Instruction:
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"""Global instruction information."""
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def __init__(self, name: str, architecture: int, bits: list[InstructionBit], format: InstructionFormat):
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"""Initialize with given parameters."""
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self.name = name
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self.architecture = architecture
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self.bits = bits.copy()
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self.format = format
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instructions = {
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Symbol.ADD: Instruction(
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"Add Word",
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1,
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[
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InstructionBit(31, 26, InstructionSegment.special),
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InstructionBit(25, 21, InstructionSegment.rs),
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InstructionBit(20, 16, InstructionSegment.rt),
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InstructionBit(15, 11, InstructionSegment.rd),
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InstructionBit(10, 6, InstructionSegment.static, "00000"),
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InstructionBit(5, 0, InstructionSegment.static, "100000"),
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],
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InstructionFormat("ADD", [InstructionSegment.rd, InstructionSegment.rs, InstructionSegment.rt]),
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),
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Symbol.ADDI: Instruction(
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"Add Immediate Word",
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1,
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[
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InstructionBit(31, 26, InstructionSegment.static, "001000"),
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InstructionBit(25, 21, InstructionSegment.rs),
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InstructionBit(20, 16, InstructionSegment.rt),
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InstructionBit(15, 0, InstructionSegment.immediate),
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],
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InstructionFormat("ADDI", [InstructionSegment.rt, InstructionSegment.rs, InstructionSegment.immediate]),
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),
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Symbol.ADDIU: Instruction(
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"Add Immediate Unsigned Word",
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1,
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[
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InstructionBit(31, 26, InstructionSegment.static, "001001"),
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InstructionBit(25, 21, InstructionSegment.rs),
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InstructionBit(20, 16, InstructionSegment.rt),
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InstructionBit(15, 0, InstructionSegment.immediate),
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],
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InstructionFormat("ADDIU", [InstructionSegment.rt, InstructionSegment.rs, InstructionSegment.immediate]),
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),
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Symbol.ADDU: Instruction(
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"Add Unsigned Word",
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1,
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[
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InstructionBit(31, 26, InstructionSegment.special),
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InstructionBit(25, 21, InstructionSegment.rs),
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InstructionBit(20, 16, InstructionSegment.rt),
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InstructionBit(15, 11, InstructionSegment.rd),
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InstructionBit(10, 6, InstructionSegment.static, "00000"),
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InstructionBit(5, 0, InstructionSegment.static, "100001"),
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],
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InstructionFormat("ADDU", [InstructionSegment.rd, InstructionSegment.rs, InstructionSegment.rt]),
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),
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Symbol.AND: Instruction(
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"And",
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1,
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[
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InstructionBit(31, 26, InstructionSegment.special),
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InstructionBit(25, 21, InstructionSegment.rs),
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InstructionBit(20, 16, InstructionSegment.rt),
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InstructionBit(15, 11, InstructionSegment.rd),
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InstructionBit(10, 6, InstructionSegment.static, "00000"),
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InstructionBit(5, 0, InstructionSegment.static, "100100"),
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],
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InstructionFormat("AND", [InstructionSegment.rd, InstructionSegment.rs, InstructionSegment.rt]),
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),
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Symbol.ANDI: Instruction(
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"And Immediate",
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1,
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[
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InstructionBit(31, 26, InstructionSegment.static, "001100"),
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InstructionBit(25, 21, InstructionSegment.rs),
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InstructionBit(20, 16, InstructionSegment.rt),
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InstructionBit(15, 0, InstructionSegment.immediate),
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],
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InstructionFormat("ANDI", [InstructionSegment.rt, InstructionSegment.rs, InstructionSegment.immediate]),
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),
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Symbol.BEQ: Instruction(
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"Branch on Equal",
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1,
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[
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InstructionBit(31, 26, InstructionSegment.static, "000100"),
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InstructionBit(25, 21, InstructionSegment.rs),
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InstructionBit(20, 16, InstructionSegment.rt),
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InstructionBit(15, 0, InstructionSegment.offset),
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],
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InstructionFormat("BEQ", [InstructionSegment.rs, InstructionSegment.rt, InstructionSegment.offset]),
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),
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Symbol.BEQL: Instruction(
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"Branch on Equal Likely",
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2,
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[
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InstructionBit(31, 26, InstructionSegment.static, "010100"),
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InstructionBit(25, 21, InstructionSegment.rs),
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InstructionBit(20, 16, InstructionSegment.rt),
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InstructionBit(15, 0, InstructionSegment.offset),
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],
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InstructionFormat("BEQL", [InstructionSegment.rs, InstructionSegment.rt, InstructionSegment.offset]),
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),
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Symbol.BGEZ: Instruction(
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"Branch on Greater Than or Equal to Zero",
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1,
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[
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InstructionBit(31, 26, InstructionSegment.regimm),
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InstructionBit(25, 21, InstructionSegment.rs),
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InstructionBit(20, 16, InstructionSegment.static, "00001"),
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InstructionBit(15, 0, InstructionSegment.offset),
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],
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InstructionFormat("BGEZ", [InstructionSegment.rs, InstructionSegment.offset]),
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),
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Symbol.BGEZAL: Instruction(
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"Branch on Greater Than or Equal to Zero and Link",
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1,
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[
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InstructionBit(31, 26, InstructionSegment.regimm),
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InstructionBit(25, 21, InstructionSegment.rs),
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InstructionBit(20, 16, InstructionSegment.static, "10001"),
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InstructionBit(15, 0, InstructionSegment.offset),
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],
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InstructionFormat("BGEZAL", [InstructionSegment.rs, InstructionSegment.offset]),
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),
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Symbol.BGEZALL: Instruction(
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"Branch on Greater Than or Equal to Zero and Link Likely",
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2,
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[
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InstructionBit(31, 26, InstructionSegment.regimm),
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InstructionBit(25, 21, InstructionSegment.rs),
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InstructionBit(20, 16, InstructionSegment.static, "10011"),
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InstructionBit(15, 0, InstructionSegment.offset),
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],
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InstructionFormat("BGEZALL", [InstructionSegment.rs, InstructionSegment.offset]),
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),
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Symbol.BGEZL: Instruction(
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"Branch on Greater Than or Equal to Zero Likely",
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2,
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[
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InstructionBit(31, 26, InstructionSegment.regimm),
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InstructionBit(25, 21, InstructionSegment.rs),
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InstructionBit(20, 16, InstructionSegment.static, "00011"),
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InstructionBit(15, 0, InstructionSegment.offset),
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],
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InstructionFormat("BGEZL", [InstructionSegment.rs, InstructionSegment.offset]),
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),
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Symbol.BGTZ: Instruction(
|
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"Branch on Greater Than Zero",
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1,
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[
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InstructionBit(31, 26, InstructionSegment.static, "000111"),
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InstructionBit(25, 21, InstructionSegment.rs),
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InstructionBit(20, 16, InstructionSegment.static, "00000"),
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InstructionBit(15, 0, InstructionSegment.offset),
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],
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InstructionFormat("BGTZ", [InstructionSegment.rs, InstructionSegment.offset]),
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),
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Symbol.BGTZL: Instruction(
|
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"Branch on Greater Than Zero Likely",
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2,
|
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[
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InstructionBit(31, 26, InstructionSegment.static, "010111"),
|
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InstructionBit(25, 21, InstructionSegment.rs),
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InstructionBit(20, 16, InstructionSegment.static, "00000"),
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InstructionBit(15, 0, InstructionSegment.offset),
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],
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InstructionFormat("BGTZL", [InstructionSegment.rs, InstructionSegment.offset]),
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),
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Symbol.BLEZ: Instruction(
|
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"Branch on Less Than or Equal to Zero",
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1,
|
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[
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InstructionBit(31, 26, InstructionSegment.static, "000110"),
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InstructionBit(25, 21, InstructionSegment.rs),
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InstructionBit(20, 16, InstructionSegment.static, "00000"),
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InstructionBit(15, 0, InstructionSegment.offset),
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],
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InstructionFormat("BLEZ", [InstructionSegment.rs, InstructionSegment.offset]),
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),
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Symbol.BLEZL: Instruction(
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"Branch on Less Than or Equal to Zero Likely",
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2,
|
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[
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InstructionBit(31, 26, InstructionSegment.static, "010110"),
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InstructionBit(25, 21, InstructionSegment.rs),
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InstructionBit(20, 16, InstructionSegment.static, "00000"),
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InstructionBit(15, 0, InstructionSegment.offset),
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],
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InstructionFormat("BLEZL", [InstructionSegment.rs, InstructionSegment.offset]),
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),
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Symbol.BLTZ: Instruction(
|
|
"Branch on Less Than Zero",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.regimm),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.static, "00000"),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("BLTZ", [InstructionSegment.rs, InstructionSegment.offset]),
|
|
),
|
|
Symbol.BLTZAL: Instruction(
|
|
"Branch on Less Than Zero And Link",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.regimm),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.static, "10000"),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("BLTZAL", [InstructionSegment.rs, InstructionSegment.offset]),
|
|
),
|
|
Symbol.BLTZALL: Instruction(
|
|
"Branch on Less Than Zero And Link Likely",
|
|
2,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.regimm),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.static, "10010"),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("BLTZALL", [InstructionSegment.rs, InstructionSegment.offset]),
|
|
),
|
|
Symbol.BLTZL: Instruction(
|
|
"Branch on Less Than Zero Likely",
|
|
2,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.regimm),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.static, "00010"),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("BLTZL", [InstructionSegment.rs, InstructionSegment.offset]),
|
|
),
|
|
Symbol.BNE: Instruction(
|
|
"Branch on Not Equal",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "000101"),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("BNE", [InstructionSegment.rs, InstructionSegment.rt, InstructionSegment.offset]),
|
|
),
|
|
Symbol.BNEL: Instruction(
|
|
"Branch on Not Equal Likely",
|
|
2,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "010101"),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("BNEL", [InstructionSegment.rs, InstructionSegment.rt, InstructionSegment.offset]),
|
|
),
|
|
Symbol.BREAK: Instruction(
|
|
"Breakpoint",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 6, InstructionSegment.code),
|
|
InstructionBit(5, 0, InstructionSegment.static, "001101"),
|
|
],
|
|
InstructionFormat("BREAK", []),
|
|
),
|
|
Symbol.COP0: Instruction(
|
|
"Coprocessor Operation",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "010000"),
|
|
InstructionBit(25, 0, InstructionSegment.cop_fun),
|
|
],
|
|
InstructionFormat("COP0", [InstructionSegment.cop_fun]),
|
|
),
|
|
Symbol.COP1: Instruction(
|
|
"Coprocessor Operation",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "010001"),
|
|
InstructionBit(25, 0, InstructionSegment.cop_fun),
|
|
],
|
|
InstructionFormat("COP1", [InstructionSegment.cop_fun]),
|
|
),
|
|
Symbol.COP2: Instruction(
|
|
"Coprocessor Operation",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "010010"),
|
|
InstructionBit(25, 0, InstructionSegment.cop_fun),
|
|
],
|
|
InstructionFormat("COP2", [InstructionSegment.cop_fun]),
|
|
),
|
|
Symbol.COP3: Instruction(
|
|
"Coprocessor Operation",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "010011"),
|
|
InstructionBit(25, 0, InstructionSegment.cop_fun),
|
|
],
|
|
InstructionFormat("COP3", [InstructionSegment.cop_fun]),
|
|
),
|
|
Symbol.DADD: Instruction(
|
|
"Doubleword Add",
|
|
3,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 11, InstructionSegment.rd),
|
|
InstructionBit(10, 6, InstructionSegment.static, "00000"),
|
|
InstructionBit(5, 0, InstructionSegment.static, "101100"),
|
|
],
|
|
InstructionFormat("DADD", [InstructionSegment.rd, InstructionSegment.rs, InstructionSegment.rt]),
|
|
),
|
|
Symbol.DADDI: Instruction(
|
|
"Doubleword Add Immediate",
|
|
3,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "011000"),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.immediate),
|
|
],
|
|
InstructionFormat("DADDI", [InstructionSegment.rt, InstructionSegment.rs, InstructionSegment.immediate]),
|
|
),
|
|
Symbol.DADDIU: Instruction(
|
|
"Doubleword Add Immediate Unsigned",
|
|
3,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "011001"),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.immediate),
|
|
],
|
|
InstructionFormat("DADDIU", [InstructionSegment.rt, InstructionSegment.rs, InstructionSegment.immediate]),
|
|
),
|
|
Symbol.DADDU: Instruction(
|
|
"Doubleword Add Unsigned",
|
|
3,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 11, InstructionSegment.rd),
|
|
InstructionBit(10, 6, InstructionSegment.static, "00000"),
|
|
InstructionBit(5, 0, InstructionSegment.static, "101101"),
|
|
],
|
|
InstructionFormat("DADDU", [InstructionSegment.rd, InstructionSegment.rs, InstructionSegment.rt]),
|
|
),
|
|
Symbol.DDIV: Instruction(
|
|
"Doubleword Divide",
|
|
3,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 6, InstructionSegment.static, "0000000000"),
|
|
InstructionBit(5, 0, InstructionSegment.static, "011110"),
|
|
],
|
|
InstructionFormat("DDIV", [InstructionSegment.rs, InstructionSegment.rt]),
|
|
),
|
|
Symbol.DDIVU: Instruction(
|
|
"Doubleword Divide Unsigned",
|
|
3,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 6, InstructionSegment.static, "0000000000"),
|
|
InstructionBit(5, 0, InstructionSegment.static, "011111"),
|
|
],
|
|
InstructionFormat("DDIVU", [InstructionSegment.rs, InstructionSegment.rt]),
|
|
),
|
|
Symbol.DIV: Instruction(
|
|
"Divide Word",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 6, InstructionSegment.static, "0000000000"),
|
|
InstructionBit(5, 0, InstructionSegment.static, "011010"),
|
|
],
|
|
InstructionFormat("DIV", [InstructionSegment.rs, InstructionSegment.rt]),
|
|
),
|
|
Symbol.DIVU: Instruction(
|
|
"Divide Unsigned Word",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 6, InstructionSegment.static, "0000000000"),
|
|
InstructionBit(5, 0, InstructionSegment.static, "011011"),
|
|
],
|
|
InstructionFormat("DIVU", [InstructionSegment.rs, InstructionSegment.rt]),
|
|
),
|
|
Symbol.DMULT: Instruction(
|
|
"Doubleword Multiply",
|
|
3,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 6, InstructionSegment.static, "0000000000"),
|
|
InstructionBit(5, 0, InstructionSegment.static, "011100"),
|
|
],
|
|
InstructionFormat("DMULT", [InstructionSegment.rs, InstructionSegment.rt]),
|
|
),
|
|
Symbol.DMULTU: Instruction(
|
|
"Doubleword Multiply Unsigned",
|
|
3,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 6, InstructionSegment.static, "0000000000"),
|
|
InstructionBit(5, 0, InstructionSegment.static, "011101"),
|
|
],
|
|
InstructionFormat("DMULTU", [InstructionSegment.rs, InstructionSegment.rt]),
|
|
),
|
|
Symbol.DSLL: Instruction(
|
|
"Doubleword Shift Left Logical",
|
|
3,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.static, "00000"),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 11, InstructionSegment.rd),
|
|
InstructionBit(10, 6, InstructionSegment.sa),
|
|
InstructionBit(5, 0, InstructionSegment.static, "111000"),
|
|
],
|
|
InstructionFormat("DSLL", [InstructionSegment.rd, InstructionSegment.rt, InstructionSegment.sa]),
|
|
),
|
|
Symbol.DSLL32: Instruction(
|
|
"Doubleword Shift Left Logical Plus 32",
|
|
3,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.static, "00000"),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 11, InstructionSegment.rd),
|
|
InstructionBit(10, 6, InstructionSegment.sa),
|
|
InstructionBit(5, 0, InstructionSegment.static, "111100"),
|
|
],
|
|
InstructionFormat("DSLL32", [InstructionSegment.rd, InstructionSegment.rt, InstructionSegment.sa]),
|
|
),
|
|
Symbol.DSLLV: Instruction(
|
|
"Doubleword Shift Left Logical Variable",
|
|
3,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 11, InstructionSegment.rd),
|
|
InstructionBit(10, 6, InstructionSegment.static, "00000"),
|
|
InstructionBit(5, 0, InstructionSegment.static, "010100"),
|
|
],
|
|
InstructionFormat("DSLLV", [InstructionSegment.rd, InstructionSegment.rt, InstructionSegment.rs]),
|
|
),
|
|
Symbol.DSRA: Instruction(
|
|
"Doubleword Shift Right Arithmetic",
|
|
3,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.static, "00000"),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 11, InstructionSegment.rd),
|
|
InstructionBit(10, 6, InstructionSegment.sa),
|
|
InstructionBit(5, 0, InstructionSegment.static, "111011"),
|
|
],
|
|
InstructionFormat("DSRA", [InstructionSegment.rd, InstructionSegment.rt, InstructionSegment.sa]),
|
|
),
|
|
Symbol.DSRA32: Instruction(
|
|
"Doubleword Shift Right Arithmetic Plus 32",
|
|
3,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.static, "00000"),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 11, InstructionSegment.rd),
|
|
InstructionBit(10, 6, InstructionSegment.sa),
|
|
InstructionBit(5, 0, InstructionSegment.static, "111111"),
|
|
],
|
|
InstructionFormat("DSRA32", [InstructionSegment.rd, InstructionSegment.rt, InstructionSegment.sa]),
|
|
),
|
|
Symbol.DSRAV: Instruction(
|
|
"Doubleword Shift Right Arithmetic Variable",
|
|
3,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 11, InstructionSegment.rd),
|
|
InstructionBit(10, 6, InstructionSegment.static, "00000"),
|
|
InstructionBit(5, 0, InstructionSegment.static, "010111"),
|
|
],
|
|
InstructionFormat("DSRAV", [InstructionSegment.rd, InstructionSegment.rt, InstructionSegment.rs]),
|
|
),
|
|
Symbol.DSRL: Instruction(
|
|
"Doubleword Shift Right Logical",
|
|
3,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.static, "00000"),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 11, InstructionSegment.rd),
|
|
InstructionBit(10, 6, InstructionSegment.sa),
|
|
InstructionBit(5, 0, InstructionSegment.static, "111010"),
|
|
],
|
|
InstructionFormat("DSRL", [InstructionSegment.rd, InstructionSegment.rt, InstructionSegment.sa]),
|
|
),
|
|
Symbol.DSRL32: Instruction(
|
|
"Doubleword Shift Right Logical Plus 32",
|
|
3,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.static, "00000"),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 11, InstructionSegment.rd),
|
|
InstructionBit(10, 6, InstructionSegment.sa),
|
|
InstructionBit(5, 0, InstructionSegment.static, "111110"),
|
|
],
|
|
InstructionFormat("DSRL32", [InstructionSegment.rd, InstructionSegment.rt, InstructionSegment.sa]),
|
|
),
|
|
Symbol.DSRLV: Instruction(
|
|
"Doubleword Shift Right Logical Variable",
|
|
3,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 11, InstructionSegment.rd),
|
|
InstructionBit(10, 6, InstructionSegment.static, "00000"),
|
|
InstructionBit(5, 0, InstructionSegment.static, "010110"),
|
|
],
|
|
InstructionFormat("DSRLV", [InstructionSegment.rd, InstructionSegment.rt, InstructionSegment.rs]),
|
|
),
|
|
Symbol.DSUB: Instruction(
|
|
"Doubleword Subtract",
|
|
3,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 11, InstructionSegment.rd),
|
|
InstructionBit(10, 6, InstructionSegment.static, "00000"),
|
|
InstructionBit(5, 0, InstructionSegment.static, "101110"),
|
|
],
|
|
InstructionFormat("DSUB", [InstructionSegment.rd, InstructionSegment.rs, InstructionSegment.rt]),
|
|
),
|
|
Symbol.DSUBU: Instruction(
|
|
"Doubleword Subtract Unsigned",
|
|
3,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 11, InstructionSegment.rd),
|
|
InstructionBit(10, 6, InstructionSegment.static, "00000"),
|
|
InstructionBit(5, 0, InstructionSegment.static, "101111"),
|
|
],
|
|
InstructionFormat("DSUBU", [InstructionSegment.rd, InstructionSegment.rs, InstructionSegment.rt]),
|
|
),
|
|
Symbol.J: Instruction(
|
|
"Jump",
|
|
1,
|
|
[InstructionBit(31, 26, InstructionSegment.static, "000010"), InstructionBit(25, 0, InstructionSegment.target)],
|
|
InstructionFormat("J", [InstructionSegment.target]),
|
|
),
|
|
Symbol.JAL: Instruction(
|
|
"Jump And Link",
|
|
1,
|
|
[InstructionBit(31, 26, InstructionSegment.static, "000011"), InstructionBit(25, 0, InstructionSegment.target)],
|
|
InstructionFormat("JAL", [InstructionSegment.target]),
|
|
),
|
|
Symbol.JALR: Instruction(
|
|
"Jump And Link Register",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.static, "00000"),
|
|
InstructionBit(15, 11, InstructionSegment.rd),
|
|
InstructionBit(10, 6, InstructionSegment.static, "00000"),
|
|
InstructionBit(5, 0, InstructionSegment.static, "001001"),
|
|
],
|
|
InstructionFormat("JALR", [InstructionSegment.rd, InstructionSegment.rs]),
|
|
),
|
|
Symbol.JR: Instruction(
|
|
"Jump Register",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 6, InstructionSegment.static, "000000000000000"),
|
|
InstructionBit(5, 0, InstructionSegment.static, "001000"),
|
|
],
|
|
InstructionFormat("JR", [InstructionSegment.rs]),
|
|
),
|
|
Symbol.LB: Instruction(
|
|
"Load Byte",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "100000"),
|
|
InstructionBit(25, 21, InstructionSegment.base),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("LB", [InstructionSegment.rt, InstructionSegment.offset, InstructionSegment.base]),
|
|
),
|
|
Symbol.LBU: Instruction(
|
|
"Load Byte Unsigned",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "100100"),
|
|
InstructionBit(25, 21, InstructionSegment.base),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("LBU", [InstructionSegment.rt, InstructionSegment.offset, InstructionSegment.base]),
|
|
),
|
|
Symbol.LD: Instruction(
|
|
"Load Doubleword",
|
|
3,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "110111"),
|
|
InstructionBit(25, 21, InstructionSegment.base),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("LD", [InstructionSegment.rt, InstructionSegment.offset, InstructionSegment.base]),
|
|
),
|
|
Symbol.LDC1: Instruction(
|
|
"Load Doubleword to Coprocessor",
|
|
2,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "110101"),
|
|
InstructionBit(25, 21, InstructionSegment.base),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("LDC1", [InstructionSegment.rt, InstructionSegment.offset, InstructionSegment.base]),
|
|
),
|
|
Symbol.LDC2: Instruction(
|
|
"Load Doubleword to Coprocessor",
|
|
2,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "110110"),
|
|
InstructionBit(25, 21, InstructionSegment.base),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("LDC2", [InstructionSegment.rt, InstructionSegment.offset, InstructionSegment.base]),
|
|
),
|
|
Symbol.LDL: Instruction(
|
|
"Load Doubleword Left",
|
|
3,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "011010"),
|
|
InstructionBit(25, 21, InstructionSegment.base),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("LDL", [InstructionSegment.rt, InstructionSegment.offset, InstructionSegment.base]),
|
|
),
|
|
Symbol.LDR: Instruction(
|
|
"Load Doubleword Right",
|
|
3,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "011011"),
|
|
InstructionBit(25, 21, InstructionSegment.base),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("LDR", [InstructionSegment.rt, InstructionSegment.offset, InstructionSegment.base]),
|
|
),
|
|
Symbol.LH: Instruction(
|
|
"Load Halfword",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "100001"),
|
|
InstructionBit(25, 21, InstructionSegment.base),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("LH", [InstructionSegment.rt, InstructionSegment.offset, InstructionSegment.base]),
|
|
),
|
|
Symbol.LHU: Instruction(
|
|
"Load Halfword Unsigned",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "100101"),
|
|
InstructionBit(25, 21, InstructionSegment.base),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("LHU", [InstructionSegment.rt, InstructionSegment.offset, InstructionSegment.base]),
|
|
),
|
|
Symbol.LL: Instruction(
|
|
"Load Linked Word",
|
|
2,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "110000"),
|
|
InstructionBit(25, 21, InstructionSegment.base),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("LL", [InstructionSegment.rt, InstructionSegment.offset, InstructionSegment.base]),
|
|
),
|
|
Symbol.LLD: Instruction(
|
|
"Load Linked Doubleword",
|
|
3,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "110100"),
|
|
InstructionBit(25, 21, InstructionSegment.base),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("LLD", [InstructionSegment.rt, InstructionSegment.offset, InstructionSegment.base]),
|
|
),
|
|
Symbol.LUI: Instruction(
|
|
"Load Upper Immediate",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "001111"),
|
|
InstructionBit(25, 21, InstructionSegment.static, "00000"),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.immediate),
|
|
],
|
|
InstructionFormat("LUI", [InstructionSegment.rt, InstructionSegment.immediate]),
|
|
),
|
|
Symbol.LW: Instruction(
|
|
"Load Word",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "100011"),
|
|
InstructionBit(25, 21, InstructionSegment.base),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("LW", [InstructionSegment.rt, InstructionSegment.offset, InstructionSegment.base]),
|
|
),
|
|
Symbol.LWC1: Instruction(
|
|
"Load Word To Coprocessor",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "110001"),
|
|
InstructionBit(25, 21, InstructionSegment.base),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("LWC1", [InstructionSegment.rt, InstructionSegment.offset, InstructionSegment.base]),
|
|
),
|
|
Symbol.LWC2: Instruction(
|
|
"Load Word To Coprocessor",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "110010"),
|
|
InstructionBit(25, 21, InstructionSegment.base),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("LWC2", [InstructionSegment.rt, InstructionSegment.offset, InstructionSegment.base]),
|
|
),
|
|
Symbol.LWC3: Instruction(
|
|
"Load Word To Coprocessor",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "110011"),
|
|
InstructionBit(25, 21, InstructionSegment.base),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("LWC3", [InstructionSegment.rt, InstructionSegment.offset, InstructionSegment.base]),
|
|
),
|
|
Symbol.LWL: Instruction(
|
|
"Load Word Left",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "100010"),
|
|
InstructionBit(25, 21, InstructionSegment.base),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("LWL", [InstructionSegment.rt, InstructionSegment.offset, InstructionSegment.base]),
|
|
),
|
|
Symbol.LWR: Instruction(
|
|
"Load Word Right",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "100110"),
|
|
InstructionBit(25, 21, InstructionSegment.base),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("LWR", [InstructionSegment.rt, InstructionSegment.offset, InstructionSegment.base]),
|
|
),
|
|
Symbol.LWU: Instruction(
|
|
"Load Word Unsigned",
|
|
3,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "100111"),
|
|
InstructionBit(25, 21, InstructionSegment.base),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("LWU", [InstructionSegment.rt, InstructionSegment.offset, InstructionSegment.base]),
|
|
),
|
|
Symbol.MFHI: Instruction(
|
|
"Move From HI Register",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 16, InstructionSegment.static, "0000000000"),
|
|
InstructionBit(15, 11, InstructionSegment.rd),
|
|
InstructionBit(10, 6, InstructionSegment.static, "00000"),
|
|
InstructionBit(5, 0, InstructionSegment.static, "010000"),
|
|
],
|
|
InstructionFormat("MFHI", [InstructionSegment.rd]),
|
|
),
|
|
Symbol.MFLO: Instruction(
|
|
"Move From LO Register",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 16, InstructionSegment.static, "0000000000"),
|
|
InstructionBit(15, 11, InstructionSegment.rd),
|
|
InstructionBit(10, 6, InstructionSegment.static, "00000"),
|
|
InstructionBit(5, 0, InstructionSegment.static, "010010"),
|
|
],
|
|
InstructionFormat("MFLO", [InstructionSegment.rd]),
|
|
),
|
|
Symbol.MOVN: Instruction(
|
|
"Move Conditional on Not Zero",
|
|
4,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 11, InstructionSegment.rd),
|
|
InstructionBit(10, 6, InstructionSegment.static, "00000"),
|
|
InstructionBit(5, 0, InstructionSegment.static, "001011"),
|
|
],
|
|
InstructionFormat("MOVN", [InstructionSegment.rd, InstructionSegment.rs, InstructionSegment.rt]),
|
|
),
|
|
Symbol.MOVZ: Instruction(
|
|
"Move Conditional on Zero",
|
|
4,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 11, InstructionSegment.rd),
|
|
InstructionBit(10, 6, InstructionSegment.static, "00000"),
|
|
InstructionBit(5, 0, InstructionSegment.static, "001010"),
|
|
],
|
|
InstructionFormat("MOVZ", [InstructionSegment.rd, InstructionSegment.rs, InstructionSegment.rt]),
|
|
),
|
|
Symbol.MTHI: Instruction(
|
|
"Move To HI Register",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 6, InstructionSegment.static, "000000000000000"),
|
|
InstructionBit(5, 0, InstructionSegment.static, "010001"),
|
|
],
|
|
InstructionFormat("MTHI", [InstructionSegment.rs]),
|
|
),
|
|
Symbol.MTLO: Instruction(
|
|
"Move To LO Register",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 6, InstructionSegment.static, "000000000000000"),
|
|
InstructionBit(5, 0, InstructionSegment.static, "010011"),
|
|
],
|
|
InstructionFormat("MTLO", [InstructionSegment.rs]),
|
|
),
|
|
Symbol.MULT: Instruction(
|
|
"Multiply Word",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 6, InstructionSegment.static, "0000000000"),
|
|
InstructionBit(5, 0, InstructionSegment.static, "011000"),
|
|
],
|
|
InstructionFormat("MULT", [InstructionSegment.rs, InstructionSegment.rt]),
|
|
),
|
|
Symbol.MULTU: Instruction(
|
|
"Multiply Unsigned Word",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 6, InstructionSegment.static, "0000000000"),
|
|
InstructionBit(5, 0, InstructionSegment.static, "011001"),
|
|
],
|
|
InstructionFormat("MULTU", [InstructionSegment.rs, InstructionSegment.rt]),
|
|
),
|
|
Symbol.NOR: Instruction(
|
|
"Not Or",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 11, InstructionSegment.rd),
|
|
InstructionBit(10, 6, InstructionSegment.static, "00000"),
|
|
InstructionBit(5, 0, InstructionSegment.static, "100111"),
|
|
],
|
|
InstructionFormat("NOR", [InstructionSegment.rd, InstructionSegment.rs, InstructionSegment.rt]),
|
|
),
|
|
Symbol.OR: Instruction(
|
|
"Or",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 11, InstructionSegment.rd),
|
|
InstructionBit(10, 6, InstructionSegment.static, "00000"),
|
|
InstructionBit(5, 0, InstructionSegment.static, "100101"),
|
|
],
|
|
InstructionFormat("OR", [InstructionSegment.rd, InstructionSegment.rs, InstructionSegment.rt]),
|
|
),
|
|
Symbol.ORI: Instruction(
|
|
"Or Immediate",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "001101"),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.immediate),
|
|
],
|
|
InstructionFormat("ORI", [InstructionSegment.rt, InstructionSegment.rs, InstructionSegment.immediate]),
|
|
),
|
|
Symbol.PREF: Instruction(
|
|
"Prefetch",
|
|
4,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "110011"),
|
|
InstructionBit(25, 21, InstructionSegment.base),
|
|
InstructionBit(20, 16, InstructionSegment.hint),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("PREF", [InstructionSegment.hint, InstructionSegment.offset, InstructionSegment.base]),
|
|
),
|
|
Symbol.SB: Instruction(
|
|
"Store Byte",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "101000"),
|
|
InstructionBit(25, 21, InstructionSegment.base),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("SB", [InstructionSegment.rt, InstructionSegment.offset, InstructionSegment.base]),
|
|
),
|
|
Symbol.SC: Instruction(
|
|
"Store Conditional Word",
|
|
2,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "111000"),
|
|
InstructionBit(25, 21, InstructionSegment.base),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("SC", [InstructionSegment.rt, InstructionSegment.offset, InstructionSegment.base]),
|
|
),
|
|
Symbol.SCD: Instruction(
|
|
"Store Conditional Doubleword",
|
|
3,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "111100"),
|
|
InstructionBit(25, 21, InstructionSegment.base),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("SCD", [InstructionSegment.rt, InstructionSegment.offset, InstructionSegment.base]),
|
|
),
|
|
Symbol.SD: Instruction(
|
|
"Store Doubleword",
|
|
3,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "111111"),
|
|
InstructionBit(25, 21, InstructionSegment.base),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("SD", [InstructionSegment.rt, InstructionSegment.offset, InstructionSegment.base]),
|
|
),
|
|
Symbol.SDC1: Instruction(
|
|
"Store Doubleword From Coprocessor",
|
|
2,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "111101"),
|
|
InstructionBit(25, 21, InstructionSegment.base),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("SDC1", [InstructionSegment.rt, InstructionSegment.offset, InstructionSegment.base]),
|
|
),
|
|
Symbol.SDC2: Instruction(
|
|
"Store Doubleword From Coprocessor",
|
|
2,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "111110"),
|
|
InstructionBit(25, 21, InstructionSegment.base),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("SDC2", [InstructionSegment.rt, InstructionSegment.offset, InstructionSegment.base]),
|
|
),
|
|
Symbol.SDL: Instruction(
|
|
"Store Doubleword Left",
|
|
3,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "101100"),
|
|
InstructionBit(25, 21, InstructionSegment.base),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("SDL", [InstructionSegment.rt, InstructionSegment.offset, InstructionSegment.base]),
|
|
),
|
|
Symbol.SDR: Instruction(
|
|
"Store Doubleword Right",
|
|
3,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "101101"),
|
|
InstructionBit(25, 21, InstructionSegment.base),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("SDR", [InstructionSegment.rt, InstructionSegment.offset, InstructionSegment.base]),
|
|
),
|
|
Symbol.SH: Instruction(
|
|
"Store Halfword",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "101001"),
|
|
InstructionBit(25, 21, InstructionSegment.base),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("SH", [InstructionSegment.rt, InstructionSegment.offset, InstructionSegment.base]),
|
|
),
|
|
Symbol.SLL: Instruction(
|
|
"Shift Word Left Logical",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.static, "00000"),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 11, InstructionSegment.rd),
|
|
InstructionBit(10, 6, InstructionSegment.sa),
|
|
InstructionBit(5, 0, InstructionSegment.static, "000000"),
|
|
],
|
|
InstructionFormat("SLL", [InstructionSegment.rd, InstructionSegment.rt, InstructionSegment.sa]),
|
|
),
|
|
Symbol.SLLV: Instruction(
|
|
"Shift Word Left Logical Variable",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 11, InstructionSegment.rd),
|
|
InstructionBit(10, 6, InstructionSegment.static, "00000"),
|
|
InstructionBit(5, 0, InstructionSegment.static, "000100"),
|
|
],
|
|
InstructionFormat("SLLV", [InstructionSegment.rd, InstructionSegment.rt, InstructionSegment.rs]),
|
|
),
|
|
Symbol.SLT: Instruction(
|
|
"Set On Less Than",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 11, InstructionSegment.rd),
|
|
InstructionBit(10, 6, InstructionSegment.static, "00000"),
|
|
InstructionBit(5, 0, InstructionSegment.static, "101010"),
|
|
],
|
|
InstructionFormat("SLT", [InstructionSegment.rd, InstructionSegment.rs, InstructionSegment.rt]),
|
|
),
|
|
Symbol.SLTI: Instruction(
|
|
"Set on Less Than Immediate",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "001010"),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.immediate),
|
|
],
|
|
InstructionFormat("SLTI", [InstructionSegment.rt, InstructionSegment.rs, InstructionSegment.immediate]),
|
|
),
|
|
Symbol.SLTIU: Instruction(
|
|
"Set on Less Than Immediate Unsigned",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "001011"),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.immediate),
|
|
],
|
|
InstructionFormat("SLTIU", [InstructionSegment.rt, InstructionSegment.rs, InstructionSegment.immediate]),
|
|
),
|
|
Symbol.SLTU: Instruction(
|
|
"Set on Less Than Unsigned",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 11, InstructionSegment.rd),
|
|
InstructionBit(10, 6, InstructionSegment.static, "00000"),
|
|
InstructionBit(5, 0, InstructionSegment.static, "101011"),
|
|
],
|
|
InstructionFormat("SLTU", [InstructionSegment.rd, InstructionSegment.rs, InstructionSegment.rt]),
|
|
),
|
|
Symbol.SRA: Instruction(
|
|
"Shift Word Right Arithmetic",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.static, "00000"),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 11, InstructionSegment.rd),
|
|
InstructionBit(10, 6, InstructionSegment.sa),
|
|
InstructionBit(5, 0, InstructionSegment.static, "000011"),
|
|
],
|
|
InstructionFormat("SRA", [InstructionSegment.rd, InstructionSegment.rt, InstructionSegment.sa]),
|
|
),
|
|
Symbol.SRAV: Instruction(
|
|
"Shift Word Right Arithmetic Variable",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 11, InstructionSegment.rd),
|
|
InstructionBit(10, 6, InstructionSegment.static, "00000"),
|
|
InstructionBit(5, 0, InstructionSegment.static, "000111"),
|
|
],
|
|
InstructionFormat("SRAV", [InstructionSegment.rd, InstructionSegment.rt, InstructionSegment.rs]),
|
|
),
|
|
Symbol.SRL: Instruction(
|
|
"Shift Word Right Logical",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.static, "00000"),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 11, InstructionSegment.rd),
|
|
InstructionBit(10, 6, InstructionSegment.sa),
|
|
InstructionBit(5, 0, InstructionSegment.static, "000010"),
|
|
],
|
|
InstructionFormat("SRL", [InstructionSegment.rd, InstructionSegment.rt, InstructionSegment.sa]),
|
|
),
|
|
Symbol.SRLV: Instruction(
|
|
"Shift Word Right Logical Variable",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 11, InstructionSegment.rd),
|
|
InstructionBit(10, 6, InstructionSegment.static, "00000"),
|
|
InstructionBit(5, 0, InstructionSegment.static, "000110"),
|
|
],
|
|
InstructionFormat("SRLV", [InstructionSegment.rd, InstructionSegment.rt, InstructionSegment.rs]),
|
|
),
|
|
Symbol.SUB: Instruction(
|
|
"Subtract Word",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 11, InstructionSegment.rd),
|
|
InstructionBit(10, 6, InstructionSegment.static, "00000"),
|
|
InstructionBit(5, 0, InstructionSegment.static, "100010"),
|
|
],
|
|
InstructionFormat("SUB", [InstructionSegment.rd, InstructionSegment.rs, InstructionSegment.rt]),
|
|
),
|
|
Symbol.SUBU: Instruction(
|
|
"Subtract Unsigned Word",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 11, InstructionSegment.rd),
|
|
InstructionBit(10, 6, InstructionSegment.static, "00000"),
|
|
InstructionBit(5, 0, InstructionSegment.static, "100011"),
|
|
],
|
|
InstructionFormat("SUBU", [InstructionSegment.rd, InstructionSegment.rs, InstructionSegment.rt]),
|
|
),
|
|
Symbol.SW: Instruction(
|
|
"Store Word",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "101011"),
|
|
InstructionBit(25, 21, InstructionSegment.base),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("SW", [InstructionSegment.rt, InstructionSegment.offset, InstructionSegment.base]),
|
|
),
|
|
Symbol.SWC1: Instruction(
|
|
"Store Word From Coprocessor",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "111001"),
|
|
InstructionBit(25, 21, InstructionSegment.base),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("SWC1", [InstructionSegment.rt, InstructionSegment.offset, InstructionSegment.base]),
|
|
),
|
|
Symbol.SWC2: Instruction(
|
|
"Store Word From Coprocessor",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "111010"),
|
|
InstructionBit(25, 21, InstructionSegment.base),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("SWC2", [InstructionSegment.rt, InstructionSegment.offset, InstructionSegment.base]),
|
|
),
|
|
Symbol.SWC3: Instruction(
|
|
"Store Word From Coprocessor",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "111011"),
|
|
InstructionBit(25, 21, InstructionSegment.base),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("SWC3", [InstructionSegment.rt, InstructionSegment.offset, InstructionSegment.base]),
|
|
),
|
|
Symbol.SWL: Instruction(
|
|
"Store Word Left",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "101010"),
|
|
InstructionBit(25, 21, InstructionSegment.base),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("SWL", [InstructionSegment.rt, InstructionSegment.offset, InstructionSegment.base]),
|
|
),
|
|
Symbol.SWR: Instruction(
|
|
"Store Word Right",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "101110"),
|
|
InstructionBit(25, 21, InstructionSegment.base),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.offset),
|
|
],
|
|
InstructionFormat("SWR", [InstructionSegment.rt, InstructionSegment.offset, InstructionSegment.base]),
|
|
),
|
|
Symbol.SYNC: Instruction(
|
|
"Synchronize Shared Memory",
|
|
2,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 11, InstructionSegment.static, "000000000000000"),
|
|
InstructionBit(10, 6, InstructionSegment.stype),
|
|
InstructionBit(5, 0, InstructionSegment.static, "001111"),
|
|
],
|
|
InstructionFormat("SYNC", []),
|
|
),
|
|
Symbol.SYSCALL: Instruction(
|
|
"System Call",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 6, InstructionSegment.code),
|
|
InstructionBit(5, 0, InstructionSegment.static, "001100"),
|
|
],
|
|
InstructionFormat("SYSCALL", []),
|
|
),
|
|
Symbol.TEQ: Instruction(
|
|
"Trap if Equal",
|
|
2,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 6, InstructionSegment.code),
|
|
InstructionBit(5, 0, InstructionSegment.static, "110100"),
|
|
],
|
|
InstructionFormat("TEQ", [InstructionSegment.rs, InstructionSegment.rt]),
|
|
),
|
|
Symbol.TEQI: Instruction(
|
|
"Trap if Equal Immediate",
|
|
2,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.regimm),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.static, "01100"),
|
|
InstructionBit(15, 0, InstructionSegment.immediate),
|
|
],
|
|
InstructionFormat("TEQI", [InstructionSegment.rs, InstructionSegment.immediate]),
|
|
),
|
|
Symbol.TGE: Instruction(
|
|
"Trap if Greater or Equal",
|
|
2,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 6, InstructionSegment.code),
|
|
InstructionBit(5, 0, InstructionSegment.static, "110000"),
|
|
],
|
|
InstructionFormat("TGE", [InstructionSegment.rs, InstructionSegment.rt]),
|
|
),
|
|
Symbol.TGEI: Instruction(
|
|
"Trap if Greater or Equal Immediate",
|
|
2,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.regimm),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.static, "01000"),
|
|
InstructionBit(15, 0, InstructionSegment.immediate),
|
|
],
|
|
InstructionFormat("TGEI", [InstructionSegment.rs, InstructionSegment.immediate]),
|
|
),
|
|
Symbol.TGEIU: Instruction(
|
|
"Trap If Greater Or Equal Immediate Unsigned",
|
|
2,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.regimm),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.static, "01001"),
|
|
InstructionBit(15, 0, InstructionSegment.immediate),
|
|
],
|
|
InstructionFormat("TGEIU", [InstructionSegment.rs, InstructionSegment.immediate]),
|
|
),
|
|
Symbol.TGEU: Instruction(
|
|
"Trap If Greater or Equal Unsigned",
|
|
2,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 6, InstructionSegment.code),
|
|
InstructionBit(5, 0, InstructionSegment.static, "110001"),
|
|
],
|
|
InstructionFormat("TGEU", [InstructionSegment.rs, InstructionSegment.rt]),
|
|
),
|
|
Symbol.TLT: Instruction(
|
|
"Trap if Less Than",
|
|
2,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 6, InstructionSegment.code),
|
|
InstructionBit(5, 0, InstructionSegment.static, "110010"),
|
|
],
|
|
InstructionFormat("TLT", [InstructionSegment.rs, InstructionSegment.rt]),
|
|
),
|
|
Symbol.TLTI: Instruction(
|
|
"Trap if Less Than Immediate",
|
|
2,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.regimm),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.static, "01010"),
|
|
InstructionBit(15, 0, InstructionSegment.immediate),
|
|
],
|
|
InstructionFormat("TLTI", [InstructionSegment.rs, InstructionSegment.immediate]),
|
|
),
|
|
Symbol.TLTIU: Instruction(
|
|
"Trap if Less Than Immediate Unsigned",
|
|
2,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.regimm),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.static, "01011"),
|
|
InstructionBit(15, 0, InstructionSegment.immediate),
|
|
],
|
|
InstructionFormat("TLTIU", [InstructionSegment.rs, InstructionSegment.immediate]),
|
|
),
|
|
Symbol.TLTU: Instruction(
|
|
"Trap if Less Than Unsigned",
|
|
2,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 6, InstructionSegment.code),
|
|
InstructionBit(5, 0, InstructionSegment.static, "110011"),
|
|
],
|
|
InstructionFormat("TLTU", [InstructionSegment.rs, InstructionSegment.rt]),
|
|
),
|
|
Symbol.TNE: Instruction(
|
|
"Trap if Not Equal",
|
|
2,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 6, InstructionSegment.code),
|
|
InstructionBit(5, 0, InstructionSegment.static, "110110"),
|
|
],
|
|
InstructionFormat("TNE", [InstructionSegment.rs, InstructionSegment.rt]),
|
|
),
|
|
Symbol.TNEI: Instruction(
|
|
"Trap if Not Equal Immediate",
|
|
2,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.regimm),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.static, "01110"),
|
|
InstructionBit(15, 0, InstructionSegment.immediate),
|
|
],
|
|
InstructionFormat("TNEI", [InstructionSegment.rs, InstructionSegment.immediate]),
|
|
),
|
|
Symbol.XOR: Instruction(
|
|
"Exclusive OR",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.special),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 11, InstructionSegment.rd),
|
|
InstructionBit(10, 6, InstructionSegment.static, "00000"),
|
|
InstructionBit(5, 0, InstructionSegment.static, "100110"),
|
|
],
|
|
InstructionFormat("XOR", [InstructionSegment.rd, InstructionSegment.rs, InstructionSegment.rt]),
|
|
),
|
|
Symbol.XORI: Instruction(
|
|
"Exclusive OR Immediate",
|
|
1,
|
|
[
|
|
InstructionBit(31, 26, InstructionSegment.static, "001110"),
|
|
InstructionBit(25, 21, InstructionSegment.rs),
|
|
InstructionBit(20, 16, InstructionSegment.rt),
|
|
InstructionBit(15, 0, InstructionSegment.immediate),
|
|
],
|
|
InstructionFormat("XORI", [InstructionSegment.rt, InstructionSegment.rs, InstructionSegment.immediate]),
|
|
),
|
|
Symbol.NOP: Instruction(
|
|
"No Operation",
|
|
1,
|
|
[
|
|
InstructionBit(31, 0, InstructionSegment.static),
|
|
],
|
|
InstructionFormat("NOP", []),
|
|
),
|
|
}
|
|
|
|
|
|
class MIPS:
|
|
"""MIPS Instruction Parser."""
|
|
|
|
def __init__(self, symbol: Symbol, args: list):
|
|
"""Initialize with given parameters, parse."""
|
|
self.symbol = symbol
|
|
self.args = args.copy()
|
|
if self.symbol not in instructions:
|
|
raise Exception("Invalid operation")
|
|
ins = instructions[self.symbol]
|
|
arg_mapping = {}
|
|
for seg_idx in range(len(ins.format.segments)):
|
|
arg_mapping[ins.format.segments[seg_idx]] = self.args[seg_idx]
|
|
value = 0
|
|
for bit in ins.bits:
|
|
input = 0
|
|
if bit.bit_type in arg_mapping:
|
|
input = int(arg_mapping[bit.bit_type])
|
|
elif bit.bit_type in default_segment_value:
|
|
input = default_segment_value[bit.bit_type]
|
|
elif bit.bit_type == InstructionSegment.static:
|
|
input = bit.value
|
|
else:
|
|
raise Exception(f"Invalid seg type {bit.bit_type}")
|
|
input &= bit.filter
|
|
value |= input << bit.end_bit
|
|
self.value = value
|